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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. SN74LVC2G125 sces204q ? april 1999 ? revised march 2017 SN74LVC2G125 dual bus buffer gate with 3-state outputs 1 1 features 1 ? esd protection exceeds jesd 22 ? 2000-v human-body model ? 1000-v charged-device model ? available in the texas instruments nanofree ? package ? supports 5-v v cc operation ? inputs accept voltages to 5.5 v ? max t pd of 4.3 ns at 3.3 v ? low power consumption, 10- a max i cc ? 24-ma output drive at 3.3 v ? typical v olp (output ground bounce) < 0.8 v at v cc = 3.3 v, t a = 25 c ? typical v ohv (output v oh undershoot) > 2 v at v cc = 3.3 v, t a = 25 c ? i off supports live insertion, partial-power-down mode, and back-drive protection ? can be used as a down translator to translate inputs from a max of 5.5 v down to the v cc level ? latch-up performance exceeds 100 ma per jesd 78, class ii 2 applications ? cable modem termination systems ? high-speed data acquisition and generation ? military: radars and sonars ? motor controls: high-voltage ? power line communication modems ? ssds: internal or external ? video broadcasting and infrastructure: scalable platforms ? video broadcasting: ip-based multi-format transcoders ? video communications systems 3 description the SN74LVC2G125 device is a dual bus buffer gate, designed for 1.65-v to 5.5-v v cc operation. this device features dual line drivers with 3-state outputs. the outputs are disabled when the associated output-enable ( oe) input is high. nanofree ? package technology is a major breakthrough in ic packaging concepts, using the die as the package. to ensure the high-impedance state during power up or power down, oe should be tied to v cc through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. this device is fully specified for partial-power-down applications using i off . the i off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. device information (1) part number package body size SN74LVC2G125dctr sm8 (8) 2.95 mm 2.80 mm SN74LVC2G125dcur vssop (8) 2.30 mm 2.00 mm SN74LVC2G125yzpr dsbga (8) 1.91 mm 0.91 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. simplified schematic productfolder 1a 1y 1 2a 2 2y oe oe copyright ? 2017, texas instruments incorporated support &community tools & software technical documents ordernow
2 SN74LVC2G125 sces204q ? april 1999 ? revised march 2017 www.ti.com product folder links: SN74LVC2G125 submit documentation feedback copyright ? 1999 ? 2017, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 4 6 specifications ......................................................... 5 6.1 absolute maximum ratings ..................................... 5 6.2 esd ratings .............................................................. 5 6.3 recommended operating conditions ...................... 6 6.4 thermal information .................................................. 6 6.5 electrical characteristics ........................................... 7 6.6 switching characteristics: t a = ? 40 c to +85 c ...... 7 6.7 switching characteristics: t a = ? 40 c to +125 c .... 7 6.8 operating characteristics .......................................... 8 6.9 typical characteristics .............................................. 8 7 parameter measurement information .................. 9 8 detailed description ............................................ 10 8.1 overview ................................................................. 10 8.2 functional block diagram ....................................... 10 8.3 feature description ................................................. 10 8.4 device functional modes ........................................ 11 9 application and implementation ........................ 12 9.1 application information ............................................ 12 9.2 typical application ................................................. 12 10 power supply recommendations ..................... 13 11 layout ................................................................... 13 11.1 layout guidelines ................................................. 13 11.2 layout example .................................................... 14 12 device and documentation support ................. 15 12.1 documentation support ........................................ 15 12.2 receiving notification of documentation updates 15 12.3 community resources .......................................... 15 12.4 trademarks ........................................................... 15 12.5 electrostatic discharge caution ............................ 15 12.6 glossary ................................................................ 15 13 mechanical, packaging, and orderable information ........................................................... 15 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision p (january 2016) to revision q page ? removed ' 200-v machine model ' from features for consistency with esd ratings table. ................................................... 1 ? added orderable part numbers associated with each package. changed us8 to vssop. .................................................. 1 ? updated yzp package drawing to match mechanical drawing pinout. ................................................................................. 4 ? added yzp pin identifiers to pin function table. added ' buffer # ' to description for pins 2, 3, 5, and 6. changed ' power pin ' to ' positive supply ' ................................................................................................................................................ 4 ? added updated package thermal values based on new models. changes: r ja dct 220 - > 199.0, dcu 227 - > 217.8, yzp 102 - > 99.8. added: r jctop , r jb , jt , jb . .......................................................................................................... 6 ? added ' balanced push-pull outputs, ' ' cmos inputs, ' ' clamp diodes, ' ' partial power down, ' over-voltage tolerant inputs. ' removed bullet list. .................................................................................................................................................. 10 ? added improved layout guidelines and trace example image. ............................................................................................ 13 ? added documentation support section, receiving notification of documentation updates section, and community resources section ................................................................................................................................................................ 15 changes from revision o (january 2015) to revision p page ? added overbar for active low to 1 oe and 2 oe to the simplified schematic .......................................................................... 1 ? added t j junction temperature to the absolute maximum ratings ...................................................................................... 5 ? added overbar for active low to 1 oe and 2 oe to the functional block diagram ................................................................ 10 changes from revision n (november 2013) to revision o page ? added applications , device information table, pin functions table, esd ratings table, thermal information table, typical characteristics , feature description section, device functional modes , application and implementation section, power supply recommendations section, layout section, device and documentation support section, and mechanical, packaging, and orderable information section. ................................................................................................. 1
3 SN74LVC2G125 www.ti.com sces204q ? april 1999 ? revised march 2017 product folder links: SN74LVC2G125 submit documentation feedback copyright ? 1999 ? 2017, texas instruments incorporated changes from revision m (january 2007) to revision n page ? updated features . .................................................................................................................................................................. 1 ? updated document to new ti data sheet format. ................................................................................................................... 1 ? removed ordering information table. .................................................................................................................................... 1 ? changed max operating temperature to 125 c in recommended operating condition s table. ......................................... 6
4 SN74LVC2G125 sces204q ? april 1999 ? revised march 2017 www.ti.com product folder links: SN74LVC2G125 submit documentation feedback copyright ? 1999 ? 2017, texas instruments incorporated 5 pin configuration and functions yzp package 8-pin dsbga bottom view see mechanical drawings for dimensions. pin functions pin type description name dct, dcu yzp 1a 2 b1 i input of buffer 1 2a 5 d2 i input of buffer 2 1 oe 1 a1 i output enable for buffer 1 2 oe 7 b2 i output enable for buffer 2 1y 6 c2 o output of buffer 1 2y 3 c1 o output of buffer 2 gnd 4 d1 ? ground v cc 8 a2 ? positive supply see mechanical drawings for dimensions. dct package (top view) dcu package (top view) 1 v cc 8 1oe 2 7 1a 2oe 3 6 2y 1y 4 5 gnd 2a 3 6 1y 2y 8 1 v cc 1oe 5 gnd 4 2a 2 7 2oe 1a 1 2 d c b a not to scale gnd 2a 2y 1y 1a 2oe 1oe v cc
5 SN74LVC2G125 www.ti.com sces204q ? april 1999 ? revised march 2017 product folder links: SN74LVC2G125 submit documentation feedback copyright ? 1999 ? 2017, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) the input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. (3) the value of v cc is provided in the recommended operating conditions table. 6 specifications 6.1 absolute maximum ratings see (1) min max unit v cc supply voltage ? 0.5 6.5 v v i input voltage (2) ? 0.5 6.5 v v o voltage range applied to any output in the high-impedance or power-off state (2) ? 0.5 6.5 v v o voltage range applied to any output in the high or low state (2) (3) ? 0.5 v cc + 0.5 v i ik input clamp current v i < 0 ? 50 ma i ok output clamp current v o < 0 ? 50 ma i o continuous output current 50 ma continuous current through v cc or gnd 100 ma t j junction temperature 150 c t stg storage temperature ? 65 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.2 esd ratings value unit v (esd) electrostatic discharge human body model (hbm), per ansi/esda/jedec js-001 (1) 2000 v charged device model (cdm), per jedec specification jesd22-c101 (2) 1000
6 SN74LVC2G125 sces204q ? april 1999 ? revised march 2017 www.ti.com product folder links: SN74LVC2G125 submit documentation feedback copyright ? 1999 ? 2017, texas instruments incorporated (1) all unused inputs of the device must be held at v cc or gnd to ensure proper device operation. see implications of slow or floating cmos inputs , scba004. 6.3 recommended operating conditions over recommended operating free-air temperature range (unless otherwise noted) (1) min max unit v cc supply voltage operating 1.65 5.5 v data retention only 1.5 v ih high-level input voltage v cc = 1.65 v to 1.95 v 0.65 v cc v v cc = 2.3 v to 2.7 v 1.7 v cc = 3 v to 3.6 v 2 v cc = 4.5 v to 5.5 v 0.7 v cc v il low-level input voltage v cc = 1.65 v to 1.95 v 0.35 v cc v v cc = 2.3 v to 2.7 v 0.7 v cc = 3 v to 3.6 v 0.8 v cc = 4.5 v to 5.5 v 0.3 v cc v i input voltage 0 5.5 v v o output voltage high or low state 0 v cc v 3-state 0 5.5 i oh high-level output current v cc = 1.65 v ? 4 ma v cc = 2.3 v ? 8 v cc = 3 v ? 16 ? 24 v cc = 4.5 v ? 32 i ol low-level output current v cc = 1.65 v 4 ma v cc = 2.3 v 8 v cc = 3 v 16 24 v cc = 4.5 v 32 t/ v input transition rise or fall rate v cc = 1.8 v 0.15 v, 2.5 v 0.2 v 20 ns/v v cc = 3.3 v 0.3 v 10 v cc = 5 v 0.5 v 5 t a operating free-air temperature ? 40 125 c (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 6.4 thermal information thermal metric (1) SN74LVC2G125 unit dct (sm8) dcu (vssop) yzp (dsbga) 8 pins 8 pins 8 pins r ja junction-to-ambient thermal resistance 199.0 217.8 99.8 c/w r jctop junction-to-case (top) thermal resistance 89.5 98.3 1.0 c/w r jb junction-to-board thermal resistance 118.7 138.7 29.6 c/w jt junction-to-top characterization parameter 14.3 34.6 0.5 c/w jb junction-to-board characterization parameter 117.4 138.2 29.8 c/w
7 SN74LVC2G125 www.ti.com sces204q ? april 1999 ? revised march 2017 product folder links: SN74LVC2G125 submit documentation feedback copyright ? 1999 ? 2017, texas instruments incorporated (1) all typical values are at v cc = 3.3 v, t a = 25 c. 6.5 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions v cc t a = ? 40 c to +85 c t a = ? 40 c to +125 c unit min typ (1) max min typ (1) max v oh i oh = ? 100 a 1.65 v to 5.5 v v cc ? 0.1 v cc ? 0.1 v i oh = ? 4 ma 1.65 v 1.2 1.2 i oh = ? 8 ma 1.8 v 1.4 2.3 v 1.9 1.9 i oh = ? 16 ma 3 v 2.4 2.4 i oh = ? 24 ma 2.3 2.3 i oh = ? 32 ma 4.5 v 3.8 3.8 v ol i ol = 100 a 1.65 v to 5.5 v 0.1 0.1 v i ol = 4 ma 1.65 v 0.45 0.45 i ol = 8 ma 1.8 v 0.45 2.3 v 0.3 0.3 i ol = 16 ma 3 v 0.4 0.4 i ol = 24 ma 0.55 0.55 i ol = 32 ma 4.5 v 0.55 0.75 i i a or oe inputs v i = 5.5 v or gnd 0 to 5.5 v 5 5 a i off v i or v o = 5.5 v 0 10 10 a i oz v o = 0 to 5.5 v 3.6 v 10 10 a i cc v i = 5.5 v or gnd, i o = 0 1.65 v to 5.5 v 10 10 a i cc one input at v cc ? 0.6 v, other inputs at v cc or gnd 3 v to 5.5 v 500 500 a c i data inputs v i = v cc or gnd 3.3 v 3.5 3.5 pf control inputs 4 4 c o v o = v cc or gnd 3.3 v 6.5 6.5 pf 6.6 switching characteristics: t a = ? 40 c to +85 c over recommended operating free-air temperature range (unless otherwise noted) (see figure 3 ) parameter from (input) to (output) t a = ? 40 c to +85 c unit v cc = 1.8 v 0.15 v v cc = 2.5 v 0.2 v v cc = 3.3 v 0.3 v v cc = 5 v 0.5 v min max min max min max min max t pd a y 3.3 9.1 1.5 4.8 1.4 4.3 1 3.7 ns t en oe y 4 9.9 1.9 5.6 1.2 4.7 1.2 3.8 ns t dis oe y 1.5 11.6 1 5.8 1.4 4.6 1 3.4 ns 6.7 switching characteristics: t a = ? 40 c to +125 c over recommended operating free-air temperature range (unless otherwise noted) (see figure 3 ) parameter from (input) to (output) t a = ? 40 c to +125 c unit v cc = 1.8 v 0.15 v v cc = 2.5 v 0.2 v v cc = 3.3 v 0.3 v v cc = 5 v 0.5 v min max min max min max min max t pd a y 3.3 10.1 1.5 5.8 1.4 5.3 1 4.2 ns t en oe y 4 10.9 1.9 6.6 1.2 5.7 1.2 4.3 ns t dis oe y 1.5 12.6 1 6.8 1.4 5.6 1 3.9 ns
8 SN74LVC2G125 sces204q ? april 1999 ? revised march 2017 www.ti.com product folder links: SN74LVC2G125 submit documentation feedback copyright ? 1999 ? 2017, texas instruments incorporated 6.8 operating characteristics t a = 25 parameter test conditions v cc = 1.8 v v cc = 2.5 v v cc = 3.3 v v cc = 5 v unit typ typ typ typ c pd power dissipation capacitance outputs enabled f = 10 mhz 19 19 20 22 pf outputs disabled 2 2 2 3 6.9 typical characteristics figure 1. tpd across temperature at 3.3 v v cc figure 2. tpd across v cc at 25 c vcc - v tpd - ns 0 1 2 3 4 5 6 0 1 2 3 4 5 d002 tpd temperature - c tpd - ns -100 -50 0 50 100 150 0 0.5 1 1.5 2 2.5 d001 tpd
9 SN74LVC2G125 www.ti.com sces204q ? april 1999 ? revised march 2017 product folder links: SN74LVC2G125 submit documentation feedback copyright ? 1999 ? 2017, texas instruments incorporated 7 parameter measurement information figure 3. load circuit and voltage waveforms t h t su from output under test c (see note a) l load circuit s1 v load open gnd r l data input timing input 0 v0 v 0 v t w input 0 v input output waveform 1 s1 at v (see note b) load output waveform 2 s1 at gnd (see note b) v ol v oh 0 v? 0 v outputoutput test s1 t /t plh phl open output control v m v m v m v m v m 1.8 v 0.15 v 2.5 v 0.2 v 3.3 v 0.3 v 5 v 0.5 v 1 k w 500 w 500 w 500 w v cc r l 2 v cc 2 v cc 6 v 2 v cc v load c l 30 pf30 pf 50 pf 50 pf 0.15 v0.15 v 0.3 v0.3 v v d 3 v v i v cc /2 v cc /2 1.5 v v cc /2 v m 2 ns 2 ns 2.5 ns 2.5 ns inputs r l t /t r f v cc v cc v cc v load t /t plz pzl gnd t /t phz pzh voltage waveforms enable and disable times low- and high-level enabling voltage waveforms propagation delay times inverting and noninverting outputs notes: a. c includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. c. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z = 50 . d. the outputs are measured one at a time, with one transition per measurement. e. t and t are the same as t . f. t and t are the same as t . g. t and t are the same as t . h. all parameters and waveforms are not applicable to all devices. l o plz phz dis pzl pzh en plh phl pd w voltage waveforms pulse duration voltage waveforms setup and hold times v i v i v i v m v m v /2 load t pzl t plz t phz t pzh v C v oh d v + v ol d v m v m v m v m v ol v oh v i v i v oh v ol v m v m v m v m t plh t phl t plh t phl
10 SN74LVC2G125 sces204q ? april 1999 ? revised march 2017 www.ti.com product folder links: SN74LVC2G125 submit documentation feedback copyright ? 1999 ? 2017, texas instruments incorporated 8 detailed description 8.1 overview the SN74LVC2G125 device contains dual buffer gate device with output enable control and performs the boolean function y = a. this device is fully specified for partial-power-down applications using i off . the i off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. to ensure the high-impedance state during power up or power down, oe should be tied to v cc through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 8.2 functional block diagram 8.3 feature description 8.3.1 balanced high-drive cmos push-pull outputs a balanced output allows the device to sink and source similar currents. the high drive capability of this device creates fast edges into light loads so routing and load conditions should be considered to prevent ringing. additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. it is important for the power output of the device to be limited to avoid thermal runaway and damage due to over-current. the electrical and thermal limits defined the in the absolute maximum ratings must be followed at all times. 8.3.2 standard cmos inputs standard cmos inputs are high impedance and are typically modelled as a resistor in parallel with the input capacitance given in the electrical characteristics . the worst case resistance is calculated with the maximum input voltage, given in the absolute maximum ratings , and the maximum input leakage current, given in the electrical characteristics , using ohm's law (r = v i). signals applied to the inputs need to have fast edge rates, as defined by t/ v in recommended operating conditions to avoid excessive currents and oscillations. if a slow or noisy input signal is required, a device with a schmitt-trigger input should be utilized to condition the input signal prior to the standard cmos input. 8.3.3 clamp diodes the inputs and outputs to this device have negative clamping diodes. caution voltages beyond the values specified in the absolute maximum ratings table can cause damage to the device. the input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 1a 1y 1 2a 2 2y oe oe copyright ? 2017, texas instruments incorporated
11 SN74LVC2G125 www.ti.com sces204q ? april 1999 ? revised march 2017 product folder links: SN74LVC2G125 submit documentation feedback copyright ? 1999 ? 2017, texas instruments incorporated feature description (continued) figure 4. electrical placement of clamping diodes for each input and output 8.3.4 partial power down (i off ) the inputs and outputs for this device enter a high impedance state when the supply voltage is 0 v. the maximum leakage into or out of any input or output pin on the device is specified by i off in the electrical characteristics . 8.3.5 over-voltage tolerant inputs input signals to this device can be driven above the supply voltage so long as they remain below the maximum input voltage value specified in the absolute maximum ratings . 8.4 device functional modes table 1 lists the functional modes of the SN74LVC2G125. table 1. function table inputs output y oe a l h h l l l h x z gnd logic input output v cc device -i ik -i ok
12 SN74LVC2G125 sces204q ? april 1999 ? revised march 2017 www.ti.com product folder links: SN74LVC2G125 submit documentation feedback copyright ? 1999 ? 2017, texas instruments incorporated 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information the SN74LVC2G125 device is a high drive cmos device that can be used as a output enabled buffer with a high output drive, such as an led application. it can produce 24 ma of drive current at 3.3 v making it ideal for driving multiple outputs and good for high speed applications up to 100 mhz. the inputs are 5.5-v tolerant allowing it to translate down to v cc . 9.2 typical application figure 5. typical application schematic 9.2.1 design requirements this device uses cmos technology and has balanced output drive. take care to avoid bus contention because it can drive currents that would exceed maximum limits. the high drive also creates fast edges into light loads so routing and load conditions should be considered to prevent ringing. 9.2.2 detailed design procedure 1. recommended input conditions: ? for rise time and fall time specifications, see ( t/ v) in the recommended operating conditions table. ? for specified high and low levels, see (v ih and v il ) in the recommended operating conditions table. ? inputs are overvoltage tolerant allowing them to go as high as (v i max) in the recommended operating conditions table at any valid v cc . 2. recommended output conditions: ? load currents should not exceed (i o max) per output and should not exceed (continuous current through v cc or gnd) total current for the part. these limits are located in the absolute maximum ratings table. ? outputs should not be pulled above v cc . 1oe 1a2y gnd vcc 2oe 1y2a SN74LVC2G125 input signal 1 from system output 2 to long pcb trace or high-z logic input output 1 to long pcb trace or high-z logic input input signal 2 from system 0.1 f 1.65 v to 5 v copyright ? 2017, texas instruments incorporated
13 SN74LVC2G125 www.ti.com sces204q ? april 1999 ? revised march 2017 product folder links: SN74LVC2G125 submit documentation feedback copyright ? 1999 ? 2017, texas instruments incorporated typical application (continued) 9.2.3 application curve figure 6. i cc vs frequency 10 power supply recommendations the power supply can be any voltage between the min and max supply voltage rating located in the recommended operating conditions table. each v cc pin should have a good bypass capacitor to prevent power disturbance. for devices with a single supply a 0.1- f capacitor is recommended and if there are multiple v cc pins then a 0.01- f or 0.022- f capacitor is recommended for each power pin. it is ok to parallel multiple bypass caps to reject different frequencies of noise. 0.1- f and 1- f capacitors are commonly used in parallel. the bypass capacitor should be installed as close to the power pin as possible for best results. 11 layout 11.1 layout guidelines when using multiple bit logic devices, inputs should not float. in many cases, functions or parts of functions of digital logic devices are unused. some examples are when only two inputs of a triple-input and gate are used, or when only 3 of the 4-buffer gates are used. such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. specified in figure 7 are rules that must be observed under all circumstances. all unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. the logic level that should be applied to any particular unused input depends on the function of the device. generally they will be tied to gnd or v cc , whichever makes more sense or is more convenient. even low data rate digital signals can have high frequency signal components due to fast edge rates. when a pcb trace turns a corner at a 90 angle, a reflection can occur. a reflection occurs primarily because of the change of width of the trace. at the apex of the turn, the trace width increases to 1.414 times the width. this increase upsets the transmission-line characteristics, especially the distributed capacitance and self ? inductance of the trace which results in the reflection. not all pcb traces can be straight and therefore some traces must turn corners. figure 8 shows progressively better techniques of rounding corners. only the last example (best) maintains constant trace width and minimizes reflections. frequency (mhz) i (ma) cc 0 20 40 60 80 0 1 2 3 4 5 6 7 8 9 10 d003 v 1.8 v cc v cc 2.5 v v cc 3.3 v v cc 5 v
14 SN74LVC2G125 sces204q ? april 1999 ? revised march 2017 www.ti.com product folder links: SN74LVC2G125 submit documentation feedback copyright ? 1999 ? 2017, texas instruments incorporated 11.2 layout example figure 7. proper multi-gate input termination diagram figure 8. trace example worst better best 1w min. w 2w v cc unused input input output output input unused input
15 SN74LVC2G125 www.ti.com sces204q ? april 1999 ? revised march 2017 product folder links: SN74LVC2G125 submit documentation feedback copyright ? 1999 ? 2017, texas instruments incorporated 12 device and documentation support 12.1 documentation support 12.1.1 related documentation for related documentation see the following: implications of slow or floating cmos inputs , scba004. 12.2 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 12.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.4 trademarks nanofree, e2e are trademarks of texas instruments. 12.5 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 13 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 26-sep-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples 74lvc2g125dctre4 active sm8 dct 8 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 c25 (r, z) 74lvc2g125dctre6 active sm8 dct 8 3000 pb-free (rohs) cu snbi level-1-260c-unlim -40 to 125 c25 z 74lvc2g125dctrg4 active sm8 dct 8 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 c25 (r, z) 74lvc2g125dcure4 active vssop dcu 8 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 c25r 74lvc2g125dcurg4 active vssop dcu 8 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 c25r 74lvc2g125dcutg4 active vssop dcu 8 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 c25r SN74LVC2G125dct3 active sm8 dct 8 3000 pb-free (rohs) cu snbi level-1-260c-unlim -40 to 125 c25 z SN74LVC2G125dctr active sm8 dct 8 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 c25 (r, z) SN74LVC2G125dcu3 active vssop dcu 8 3000 pb-free (rohs) cu snbi level-1-260c-unlim -40 to 125 25 cz SN74LVC2G125dcur active vssop dcu 8 3000 green (rohs & no sb/br) cu nipdau | cu sn level-1-260c-unlim -40 to 125 (25, c25q, c25r) cz SN74LVC2G125dcut active vssop dcu 8 250 green (rohs & no sb/br) cu nipdau | cu sn level-1-260c-unlim -40 to 125 (c25q, c25r) SN74LVC2G125yzpr active dsbga yzp 8 3000 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 125 (cm7, cmn) (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption.
package option addendum www.ti.com 26-sep-2018 addendum-page 2 green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of SN74LVC2G125 : ? automotive: SN74LVC2G125-q1 note: qualified version definitions: ? automotive - q100 devices qualified for high-reliability automotive applications targeting zero defects
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant 74lvc2g125dctre6 sm8 dct 8 3000 180.0 13.0 3.35 4.5 1.55 4.0 12.0 q3 74lvc2g125dcurg4 vssop dcu 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 q3 74lvc2g125dcutg4 vssop dcu 8 250 180.0 8.4 2.25 3.35 1.05 4.0 8.0 q3 SN74LVC2G125dct3 sm8 dct 8 3000 180.0 13.0 3.35 4.5 1.55 4.0 12.0 q3 SN74LVC2G125dctr sm8 dct 8 3000 180.0 13.0 3.35 4.5 1.55 4.0 12.0 q3 SN74LVC2G125dcur vssop dcu 8 3000 180.0 9.0 2.05 3.3 1.0 4.0 8.0 q3 SN74LVC2G125yzpr dsbga yzp 8 3000 178.0 9.2 1.02 2.02 0.63 4.0 8.0 q1 package materials information www.ti.com 27-sep-2018 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) 74lvc2g125dctre6 sm8 dct 8 3000 182.0 182.0 20.0 74lvc2g125dcurg4 vssop dcu 8 3000 202.0 201.0 28.0 74lvc2g125dcutg4 vssop dcu 8 250 202.0 201.0 28.0 SN74LVC2G125dct3 sm8 dct 8 3000 182.0 182.0 20.0 SN74LVC2G125dctr sm8 dct 8 3000 182.0 182.0 20.0 SN74LVC2G125dcur vssop dcu 8 3000 182.0 182.0 20.0 SN74LVC2G125yzpr dsbga yzp 8 3000 220.0 220.0 35.0 package materials information www.ti.com 27-sep-2018 pack materials-page 2

mechanical data mpds049b ? may 1999 ? revised october 2002 post office box 655303 ? dallas, texas 75265 dct (r-pdso-g8) plastic small-outline package ????? ????? ????? ????? 0,60 0,20 0,25 0 ? 8 0,15 nom gage plane 4188781/c 09/02 4,25 5 0,30 0,15 2,90 3,75 2,70 8 4 3,15 2,75 1 0,10 0,00 1,30 max seating plane 0,10 m 0,13 0,65 pin 1 index area notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion d. falls within jedec mo-187 variation da.

www.ti.com package outline c 0.5 max 0.19 0.15 1.5 typ 0.5 typ 8x 0.25 0.21 0.5 typ b e a d 4223082/a 07/2016 dsbga - 0.5 mm max height yzp0008 die size ball grid array notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. ball a1 corner seating plane ball typ 0.05 c b 1 2 0.015 c a b symm symm c a d scale 8.000d: max = e: max = 1.918 mm, min = 0.918 mm, min = 1.858 mm0.858 mm
www.ti.com example board layout 8x ( 0.23) (0.5) typ (0.5) typ ( 0.23) metal 0.05 max ( 0.23) solder mask opening 0.05 min 4223082/a 07/2016 dsbga - 0.5 mm max height yzp0008 die size ball grid array notes: (continued) 3. final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. for more information, see texas instruments literature number snva009 (www.ti.com/lit/snva009). symm symm land pattern example scale:40x 1 2 a b c d non-solder mask defined (preferred) solder mask details not to scale solder mask opening solder mask defined metal under solder mask
www.ti.com example stencil design (0.5) typ (0.5) typ 8x ( 0.25) (r0.05) typ metal typ 4223082/a 07/2016 dsbga - 0.5 mm max height yzp0008 die size ball grid array notes: (continued) 4. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. symm symm solder paste example based on 0.1 mm thick stencil scale:40x 1 2 a b c d
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